1. Technical Field
The present invention relates to memory circuits in general, and in particular to static random access memory circuits. Still more particularly, the present invention relates to single event upset hardened static random access memory cells.
2. Description of Related Art
Static random access memories (SRAMs) that employ conventional six-transistor memory cells are commonly utilized in electronic devices for storing information. In certain environments, such as satellite orbital space, in which the level of radiation is relatively intense, SRAMs are more susceptible to single event upsets (SEUs) or soft errors.
Generally speaking, SEUs are caused by electron-hole pairs created by, and travelling along the path of, a single energetic particle as it passes through memory cells such as SRAM cells. A critical charge is the minimum amount of electrical charge required to change the logic state of an SRAM cell. Should the energetic particle generate a critical charge within a storage node of an SRAM cell, the logic state of the SRAM cell will be upset.
In accordance with a preferred embodiment of the present invention, a single event upset (SEU) hardened memory cell includes a first transistor, a second transistor and a first resistor connected between a source of the first transistor and a drain of the second transistor. The SEU hardened memory cell also includes a third transistor, a fourth transistor and a second resistor connected between a source of the third transistor and a drain of the fourth transistor. The first resistor is also connected between a gate of the third transistor and the drain of the second transistor. The second resistor is also connected between a gate of the first transistor and the drain of the fourth transistor.